ADDER X-SC Manuel d'utilisateur télécharger pdf (Page 60)

60 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLES

(a) (b) (c)

Figure 2.3: Three adder-tree schemes. (a) Wallace’s (b) Dadda’s (c) Palacios’s

Figure 2.4: Half adder (HA) circuit details.

Figure 2.5: Full adder (FA) circuit details.

full adder circuits usen in them. Details of these circuits are given in Figure 2.4 and Figure 2.5, respectively.

In this example we will implement the last stage of the multiplier with a simple ripple carry adder as the one

shown in Figure 2.6. The hierarchical structure of our multiplier is the one shown in Figure 2.7.

Figure 2.6: 4-bit ripple carry adder.

1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 86 87

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ADDER X-SC Manuel d'utilisateur Page 60